The majority of present day integrated circuits (ICs) are implemented by using a plurality of interconnected field effect transistors (FETs). A FET includes a gate electrode as a control electrode and spaced apart source and drain regions formed in a semiconductor substrate and between which a current can flow. A control voltage applied to the gate electrode controls the flow of current through a channel between the source and drain regions. Depending upon doping during the fabrication processes a FET can be an n-channel device (NFET) or a p-channel device (PFET).
One of the most important semiconductor circuits is the static random access memory (SRAM) cell used in many demanding memory applications. A six-transistor (6T) SRAM cell includes two PFETs for pull-up operation, two NFETs for pull-down, and two NFETs for input/output (i.e., passgate or transfer) access. However, conventional layouts (topologies) for a 6T SRAM cell typically share the active regions of the NFET passgate devices with the NFET pull-down devices. Such a topology does not accommodate individual electrical device threshold control, and therefore, prevents conventional topologies from gaining the advantages offered by individual electrical threshold control of the NFET devices.
Accordingly, a need exists to provide methods for fabricating an SRAM cell that provides individual electrical threshold control for the NFET devices. Additionally it is desirable to fully exploit the advantages of individual electrical device threshold control for superior SRAM performance. Furthermore, other desirable features and characteristics of the present invention will become apparent from the subsequent detailed description and the appended claims, taken in conjunction with the accompanying drawings and the foregoing technical field and background.